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4, 8 MEG x 64 DRAM SODIMMs
SMALL-OUTLINE DRAM MODULE
FEATURES
* JEDEC pinout in a 144-pin, small-outline, dual inline memory module (SODIMM) * 32MB (4 Meg x 64) and 64MB (8 Meg x 64) * High-performance CMOS silicon-gate process * Single +3.3V 0.3V power supply * All inputs, outputs and clocks are TTL-compatible * 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh distributed across 64ms * FAST PAGE MODE (FPM) or Extended Data-Out (EDO) PAGE MODE access cycles * Optional Self Refresh Mode (S) * Serial presence-detect (SPD)
MT4LDT464H (X)(S), MT8LDT864H (X)(S)
For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/datasheets/datasheet.html
PIN ASSIGNMENT (Front View) 144-Pin Small-Outline DIMM (I-1; 32MB) (I-2; 64MB)
OPTIONS
* Package 144-pin SODIMM (gold) * Timing 50ns access 60ns access * Access Cycles FAST PAGE MODE EDO PAGE MODE * Refresh Rates Standard Refresh Self Refresh (128ms period)
*Contact factory for availability
MARKING
G
-5 -6
None X
None S*
KEY TIMING PARAMETERS
FPM Operating Mode
SPEED -5 -6
tRC 90ns 110ns tRAC tPC 30ns 35ns tAA 25ns 30ns tCAC tRP 30ns 40ns
50ns 60ns
13ns 15ns
EDO Operating Mode
SPEED -5 -6
tRC tRAC tPC tAA tCAC tCAS
84ns 104ns
50ns 60ns
20ns 25ns
25ns 30ns
13ns 15ns
8ns 10ns
PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 NOTE:
FRONT VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS CAS0# CAS1# VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 DQ14 DQ15 VSS RSVD RSVD RFU VDD RFU WE# RAS0# NC
PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
BACK VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS CAS4# CAS5# VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 DQ46 DQ47 VSS RSVD RSVD RFU VDD RFU RFU NC NC
PIN 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
FRONT OE# VSS RSVD RSVD VDD DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10 VDD CAS2# CAS3# VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS SDA VDD
PIN 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
BACK RFU VSS RSVD RSVD VDD DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VDD A7 A11 VSS NC (A12) NC (A13) VDD CAS6# CAS7# VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS SCL VDD
Symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only.
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4, 8 MEG x 64 DRAM SODIMMs
PART NUMBERS
FPM Operating Mode
PART NUMBER MT4LDT464HG-x MT4LDT464HG-x S MT8LDT864HG-x MT8LDT864HG-x S x = speed CONFIGURATION 4 Meg x 64 4 Meg x 64 8 Meg x 64 8 Meg x 64 REFRESH Standard Self Standard Self
CAS#. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding RAS# LOW, thus executing faster memory cycles. Returning RAS# HIGH terminates the FAST-PAGEMODE operation.
EDO PAGE MODE
EDO PAGE MODE, designated by the "X" option, is an accelerated FAST-PAGE-MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS# goes back HIGH. EDO provides for CAS# precharge time (tCP) to occur without the output data going invalid. This elimination of CAS# output control provides for pipelined READs. FAST-PAGE-MODE modules have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO operates as any DRAM READ or FAST-PAGE-MODE READ, except data will be held valid after CAS# goes HIGH, as long as RAS# and OE# are held LOW and WE# is held HIGH. (Refer to the 8 Meg x 8 EDO DRAM data sheet for additional information on EDO functionality.)
EDO Operating Mode
PART NUMBER MT4LDT464HG-x X MT4LDT464HG-x XS MT8LDT864HG-x X MT8LDT864HG-x XS x = speed CONFIGURATION 4 Meg x 64 4 Meg x 64 8 Meg x 64 8 Meg x 64 REFRESH Standard Self Standard Self
GENERAL DESCRIPTION
The MT4LDT464H (X)(S) and MT8LDT864H (X)(S) are randomly accessed 32MB and 64MB memories organized in a small-outline, x64 configuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems. During READ or WRITE cycles, each location is uniquely addressed via the address bits. The row address is latched by the RAS# signal, then the column address is latched by the CAS# signal. READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z, regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFYWRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data outputs will drive read data from the access location.
REFRESH
Memory cell data is retained in its correct state by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# refresh cycle (RAS#-ONLY, CBR or HIDDEN) so that all combinations of RAS# addresses are executed at least every tREF, regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS# addressing. An optional self refresh mode is also available on the "S" version. The "S" option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms, or 125s per row when using distributed CBR REFESH. The optional self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW for the specified tRASS. The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-toHIGH transition. If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes a RAS#-ONLY or burst refresh sequence, all 1,240 rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation.
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data operations (READ or WRITE) within a row-addressdefined page boundary. The FAST-PAGE-MODE cycle is always initiated with a row address strobed in by RAS#, followed by a column address strobed in by
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4, 8 MEG x 64 DRAM SODIMMs
FUNCTIONAL BLOCK DIAGRAM MT4LDT464H (X) (32MB)
DQ0-DQ15 DQ16-DQ31
16
DQ0-DQ15 WE# OE# RAS0# CAS0# CAS1# CAS2# CAS3# A0-A11 WE# U1 OE# RAS# CASL# CASH# A0A11 OE# RAS# CASL#
16
DQ0-DQ15 WE# U2
CASH# A0A11
12
12
DQ32-DQ47
DQ48-DQ63
16
DQ0-DQ15 WE# U3 OE# RAS# CAS4# CAS5# CAS6# CAS7# CASL# CASH# A0A11 OE# RAS# CASL#
16
DQ0-DQ15 WE# U4
CASH# A0A11
12
12
SPD SCL SA0 SA1 SA2 SDA
U1-U4 = MT4LC4M16R6 EDO PAGE MODE U1-U4 = MT4LC4M16F5 FAST PAGE MODE VDD VSS U1-U4 U1-U4
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4, 8 MEG x 64 DRAM SODIMMs
FUNCTIONAL BLOCK DIAGRAM MT8LDT864H (X) (64MB)
DQ0-DQ7 DQ8-DQ15 DQ16-DQ23 DQ24-DQ31
8
DQ0-DQ7 WE# OE# RAS0# CAS0# WE# U1 OE# RAS# CAS# A0A11 CAS1# CAS2# CAS3# A0-A11 OE# RAS# CAS#
8
DQ0-DQ7 WE# U2 OE# RAS# CAS# A0A11
8
DQ0-DQ7 WE# U3 OE# RAS# CAS# A0A11
8
DQ0-DQ7 WE# U4
A0A11
12
12
12
12
DQ32-DQ39
DQ40-DQ47
DQ48-DQ55
DQ56-DQ63
8
DQ0-DQ7 WE# U5 OE# RAS# CAS4# CAS# A0A11 CAS5# CAS6# CAS7# OE# RAS# CAS#
8
DQ0-DQ7 WE# U6 OE# RAS# CAS# A0A11
8
DQ0-DQ7 WE# U7 OE# RAS# CAS# A0A11
8
DQ0-DQ7 WE# U8
A0A11
12
12
12
12
SPD SCL SA0 SA1 SA2 SDA
VDD VSS
U1-U8 U1-U8
U1-U8 = MT4LC8M8B6 FAST PAGE MODE U1-U8 = MT4LC8M8C2 EDO PAGE MODE
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4, 8 MEG x 64 DRAM SODIMMs
STANDBY
Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS# HIGH time. SPD START CONDITION All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD STOP CONDITION All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SPD ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (Figure 3). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presencedetect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various DRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM's SCL (clock) and SDA (data) signals. SPD CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2).
SCL
SCL
SDA
DATA STABLE DATA CHANGE DATA STABLE
SDA
START BIT
STOP BIT
Figure 1 Data Validity
Figure 2 Definition of Start and Stop
SCL from Master
8
9
Data Output from Transmitter
Data Output from Receiver Acknowledge
Figure 3 Acknowledge Response From Receiver
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4, 8 MEG x 64 DRAM SODIMMs
operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode.
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
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4, 8 MEG x 64 DRAM SODIMMs
SERIAL PRESENCE-DETECT MATRIX
BYTE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15-61 62 63 DESCRIPTION ENTRY (VERSION) BIT7 NUMBER OF BYTES USED BY MICRON 128 1 TOTAL NUMBER OF SPD MEMORY BYTES 256 0 MEMORY TYPE FAST PAGE MODE 0 EDO PAGE MODE 0 NUMBER OF ROW ADDRESSES NUMBER OF COLUMN ADDRESSES NUMBER OF BANKS MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS RAS# ACCESS TIME (tRAC) CAS# ACCESS TIME (tCAC) MODULE CONFIGURATION TYPE REFRESH RATE/TYPE15.6s/NORMAL DRAM WIDTH (PRIMARY DRAM) ERROR CHECKING DRAM DATA WIDTH RESERVED SPD REVISION CHECKSUM FOR BYTES 0-62 12 10 (32MB) 11 (64MB) 1 64 0 LVTTL 50ns (-5) 60ns (-6) 13ns (-5) 15ns (-6) NONPARITY 0 2x - 31.25s/SELF x16 (32MB) x8 (64MB) NONE REV. 0 32MB -5 (EDO) 32MB -6 (EDO) 32MB -5 (FPM) 32MB -6 (FPM) 64MB -5 (EDO) 64MB -6 (EDO) 64MB -5 (FPM) 64MB -6 (FPM) MICRON 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 x 0 0 0 0 0 x x x - BIT6 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 x 0 0 0 0 0 x x x - BIT5 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 x 0 0 0 0 0 x x x - BIT4 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 0 0 0 x 0 0 0 0 0 x x x - BIT3 0 1 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 0 0 x 0 0 0 0 0 x x x - BIT2 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 0 0 0 1 x 0 0 0 1 0 x x x - BIT1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 1 0 x 0 1 1 0 0 x x x - BIT0 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 0 00 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1 0 x 1 0 1 0 0 x x x - HEX 80 08 01 02 0C 0A 0B 01 40 00 01 32 3C 0D 0F 00 03 10 08 00 00 00 31 3D 30 3C 2A 36 29 35 2C FF 01 02 03 04 xx 01 02 03 04 00 xx xx xx -
64 65-71 72
MANUFACTURER'S JEDEC ID CODE MANUFACTURER'S JEDEC CODE (CONT.) MANUFACTURINGLOCATION
73-90 91
MODULE PART NUMBER (ASCII) PCB IDENTIFICATION CODE
92 93 94 95-98 99-125
IDENTIFICATION CODE (CONT.) YEAR OF MANUFACTURE IN BCD WEEK OF MANUFACTURE IN BCD MODULE SERIAL NUMBER MANUFACTURE SPECIFIC DATA (RSVD)
1 2 3 4 0
NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 2. x = Variable Data.
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4, 8 MEG x 64 DRAM SODIMMs
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply Relative to VSS ..................................... -1V to +4.6V Voltage on Inputs or I/O Pins Relative to VSS ................................. -1V to +4.6V Operating Temperature, TA (ambient) .. 0C to +70C Storage Temperature (plastic) ........... -55C to +125C Power Dissipation (32MB) ..................................... 4W Power Dissipation (64MB) ..................................... 8W *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input 0V VIN VDD + 0.3V (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT: DQ is disabled; 0V VOUT VDD + 0.3V OUTPUT LEVELS: Output High Voltage (IOUT = -2mA) Output Low Voltage (IOUT = 2mA) RAS0# A0-A11, WE#, OE# CAS0#-CAS7# DQ0-DQ63 SYMBOL VDD VIH VIL II1 II2 II3 IOZ VOH VOL MIN 3 2 -0.5 -16 -16 -2 -10 2.4 - MAX 3.6 VDD + 0.3 0.8 16 16 2 10 - 0.4 UNITS NOTES V V V A A A A V V 30 30 23 23
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4, 8 MEG x 64 DRAM SODIMMs
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 5, 6) (VDD = +3.3V 0.3V) PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS# = VIH) STANDBY CURRENT: CMOS (RAS# = CAS# = VDD - 0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]; tCP, tASC = 10ns) OPERATING CURRENT: EDO PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) REFRESH CURRENT: Extended ("S" version only) Average power supply current: CAS# = 0.2V or CBR cycling; RAS# = tRAS (MIN); WE# = VDD - 0.2V; A0-A11, OE# and DIN = VDD - 0.2V or 0.2V (DIN may be left open) REFRESH CURRENT: Self ("S" version only) Average power supply current: CBR with RAS# tRASS (MIN) and CAS# held LOW; WE# = VDD - 0.2V; A0-A11, OE# and DIN = VDD - 0.2V or 0.2V (DIN may be left open) SYMBOL SIZE ICC1 ICC2 32MB 64MB 32MB 64MB 32MB 64MB 32MB 64MB -5 4 8 2 4 700 1400 420 840 620 1200 700 1400 700 880 1.6 3.2 MAX -6 4 8 2 4 660 1320 380 760 500 1000 660 1320 660 800 1.6 3.2 UNITS NOTES mA mA mA 26 3, 22
ICC3
ICC4
mA
3, 22
32MB ICC5 64MB (X only) ICC6 32MB 64MB 32MB 64MB 32MB 64MB
mA
3, 22
mA
3, 22
ICC7
mA
3, 4
ICC8
mA
3, 4, 5
ICC9
32MB 64MB
1.6 2.4
1.6 2.4
mA
3, 4, 5
CAPACITANCE
PARAMETER Input Capacitance: A0-A11 Input Capacitance: WE#, OE#, RAS0# Input Capacitance: CAS0#-CAS7#, SCL Input/Output Capacitance: DQ0-DQ63 Input/Output Capacitance: SDA CI1 CI2 CI3 CIO1 CIO2
MAX SYMBOL 32MB 64MB UNITS NOTES 24 32 10 10 10 46 62 10 18 10 pF pF pF pF pF 2 2 2 2 2
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4, 8 MEG x 64 DRAM SODIMMs
FAST PAGE MODE AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 19) (VDD = +3.3V 0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# LOW to "Don't Care" during Self Refresh CAS# hold time (CBR Refresh) CAS# to output in Low-Z CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle FAST-PAGE-MODE READ or WRITE cycle time FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (FAST PAGE MODE) RAS# pulse width during Self Refresh -5 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCHD tCHR tCLZ tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH
tOFF tORD tPC tPRWC tRAC tRAD tRAH tRAS tRASP tRASS
-6 MAX 25 MIN 45 0 0 55 13 15 10 15 15 15 3 10 5 60 5 40 15 10 0 3 15 13 3 0 35 85 50 60 15 10 60 60 100 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s NOTES
MIIN 40 0 0 48 8 13 15 15 3 8 5 50 5 36 13 8 0 3 13 3 0 30 76 13 8 50 50 100
27
10,000
27 4 21 13
30
35
27 18 18
13 13
15 15
28 17, 24
15
10,000 125,000
10,000 125,000
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4, 8 MEG x 64 DRAM SODIMMs
FAST PAGE MODE AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 19) (VDD = +3.3V 0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION PARAMETER Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period (4,096 cycles) RAS# precharge time RAS# to CAS# precharge time RAS# precharge time exiting Self Refresh READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tRC tRCD tRCH tRCS tREF tRP tRPC tRPS tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWP tWRH tWRP MIN 90 18 0 0 30 0 90 0 13 131 73 13 2 8 40 0 8 10 10 MAX MIN 110 20 0 0 40 0 105 0 15 155 85 15 2 10 45 0 10 10 10 -6 MAX UNITS ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 14 16
64
64
16
27
50
50
27
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4, 8 MEG x 64 DRAM SODIMMs
EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 19) (VDD = +3.3V 0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION PARAMETER Access time from column address Column-address setup to CAS# precharge Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# LOW to "Don't Care" during Self Refresh CAS# hold time (CBR Refresh) CAS# to output in Low-Z Data output hold after next CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay -5 SYMBOL tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCHD tCHR tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH
tOEHC tOEP tOES tOFF
-6 MAX 25 MIN 15 45 0 0 49 13 15 10 10 15 10 0 3 10 5 45 5 35 10 10 0 0 10 10 5 5 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
MIN 12 38 0 0 42 8 8 15 8 0 3 8 5 38 5 28 8 8 0 0 8 5 5 4 0
27
10,000
4
13
28
35
27 18 18
12 12
15 15
28 28
12
15
17, 24
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4, 8 MEG x 64 DRAM SODIMMs
EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 19) (VDD = +3.3V 0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION PARAMETER OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (EDO PAGE MODE) RAS# pulse width during Self Refresh Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period (4,096 cycles) RAS# precharge time RAS# to CAS# precharge time RAS# precharge time exiting Self Refresh READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time Output disable delay from WE# WRITE command pulse width WE# pulse to disable at CAS# HIGH WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tORD
tPC tPRWC tRAC tRAD tRAH tRAS tRASP tRASS tRC tRCD tRCH tRCS tREF tRP tRPC tRPS tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP
-6 MAX MIN 0 25 56 50 60 12 10 60 60 100 104 14 0 0 40 5 105 0 15 140 79 15 2 10 45 0 0 5 10 10 10 MAX UNITS ns ns ns ns ns ns ns ns s ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
MIN 0 20 47 9 9 50 50 100 84 11 0 0 30 5 90 0 13 116 67 13 2 8 38 0 0 5 10 8 8
15
10,000 125,000
10,000 125,000
14 16
64
64
16
28
50
50
28
12
15
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS
(Notes: 1) (VDD = +3.3V 0.3V)
PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10% POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz SYMBOL MIN MAX VDD 3 3.6 VIH VDD x 0.7 VDD + 0.5 VIL -1 VDD x 0.3 VOL - 0.4 ILI - 10 ILO - 10 - 30 ISB ICC - 2 UNITS V V V V A A A mA NOTES
SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS
(Notes: 1) (VDD = +3.3V 0.3V)
PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR tSCL tSU:DAT tSU:STA tSU:STO tWR MIN 0.3 4.7 300 0 4 4 100 4.7 1 100 250 4.7 4.7 10 MAX 3.5 UNITS s s ns ns s s s ns s s KHz ns s s ms NOTES
300
29
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
NOTES
1. All voltages referenced to VSS. 2. This parameter is sampled. VDD = +3.3V; f = 1 MHz. 3. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100s is required after powerup, followed by eight RAS# REFRESH cycles (RAS#-ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 5ns for FPM and tT = 2.5ns for EDO. 8. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 9. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 10.If CAS# = VIH, data output is High-Z. 11.If CAS# = VIL, data output may contain data from the last valid READ cycle. 12.Measured with a load equivalent to two TTL gates and 100pF and VOL = 0.8V and VOH = 2V. 13.If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS# must be pulsed HIGH for tCP. 14.The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD (MAX) limit, tAA and tCAC must always be met. 15.The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC and tCAC must always be met. 16.Either tRCH or tRRH must be satisfied for a READ cycle. 17. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 18.These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 19.If OE# is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not permissible and should not be attempted. Additionally, with EDO, WE# must be pulsed during CAS# HIGH time in order to place I/O buffers in High-Z. 20.A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 21.The 3ns minimum is a parameter guaranteed by design. 22.Column address changed once each cycle. 23.8MB module values will be half of those shown. 24.With the FPM option, tOFF is determined by the first RAS# or CAS# signal to transition HIGH. In comparison, tOFF on an EDO option is determined by the latter of the RAS# and CAS# signals to transition HIGH. 25.Applies to both FPM and EDO operating modes. 26.All other inputs at 0.2V or VDD - 0.2V. 27. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. tRWD, tAWD and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tWCS < tWCS (MIN) and tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READMODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle.
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
NOTES (continued)
28.LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS# remains LOW and OE# is taken back LOW after tOEH is met. If CAS# goes HIGH prior to OE# going back LOW, the DQs will remain open. 29.The SPD EEPROM WRITE cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/ program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 30.VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate.
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
READ CYCLE 25
tRC tRAS V IH V IL tCSH tRSH tCRP V IH V IL tRAD tRAH tAR tASC tCAH tACH tRCD tCAS tRRH tRP
RAS#
CASL#/CASH#
tASR V IH V IL
ADDR
ROW tRCS
COLUMN tRCH
ROW
WE#
V IH V IL tAA tRAC tCAC tCLZ
NOTE 1 tOFF
DQ
V OH V OL
OPEN tOE
VALID DATA tOD
OPEN
OE#
V IH V IL
DON'T CARE UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL tAA tACH (EDO) tAR (EDO)
tASC tASR tCAC tAR
-6 MAX 25 MIN 15 45 0 0 13 15 45 10,000 10,000 10 10 15 0 3 5 45 12 13 12 60 0 3 15 15 15 10,000 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOE (FPM) tOFF (EDO) tOFF (FPM) tRAC
tRAD tRAD tRAH tRAH tRAS tRC (EDO) tRC
-5 MIN 0 3 9 13 9 8 50 84 90 11 18 0 0 30 0 13 MAX 13 12 13 50 MIN 0 3 12 15 10 10 60 104 110 14 20 0 0 40 0 15
-6 MAX 15 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 0 0 40 8 8 13 0 3 5 38 50 0 3
(EDO) (FPM) (EDO) (FPM)
(FPM) (EDO)
tCAH tCAS tCAS
10,000
10,000
(FPM) tCLZ (EDO) tCLZ (FPM)
tCRP tCSH tCSH tOD
(FPM) (EDO) (FPM)
tRCD tRCD tRCH tRCS tRP tRRH tRSH
(EDO) (FPM)
tOD (EDO)
(FPM)
tOE (EDO)
NOTE: 1. For EDO, tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. For FPM, tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs first.
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
EARLY WRITE CYCLE 25
tRC tRAS RAS# V IH V IL tCSH tRSH tCRP CASL#/CASH# V IH V IL tRAD tASR ADDR V IH V IL ROW tRAH COLUMN tCWL tRWL tWCS tWCR tWCH tWP WE# V IH V IL tDS V DQ V IOH IOL V IH V IL VALID DATA tDH tAR tASC tCAH tACH ROW tRCD tCAS tRP
OE#
DON'T CARE UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL tACH (EDO) tAR (EDO)
tAR
-6 MAX MIN 15 45 45 0 0 10 15 10 5 60 45 15 10 10 0 15 12 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tRAH (EDO) tRAH (FPM)
tRAS tRC
-5 MIN 9 8 50 90 84 18 11 30 13 13 8 38 40 0 8 5 MAX MIN 10 10 60 110 104 20 14 40 15 15 10 45 45 0 10 5
-6 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 40 0 0 8 13 8 5 50 38 13 8 8 0 -- 9
(FPM)
10,000
10,000
tASC tASR tCAH tCAS tCAS tCRP tCSH
(FPM)
tRC (EDO) tRCD tRP tRSH tRWL tWCH tWCR tWCR tWCS tWP (FPM) tWP (EDO)
(FPM) (EDO)
10,000 10,000
10,000 10,000
(FPM) tRCD (EDO)
(FPM) (EDO) tCWL (FPM)
tCSH tCWL (EDO) tDH tDS tRAD
(EDO) (FPM)
(FPM) tRAD (EDO)
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
FAST-PAGE-MODE READ CYCLE
tRASP V IH V IL tCSH tCRP CASL#/CASH# V IH V IL tAR tASR ADDR V IH V IL tRAD tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP
RAS#
ROW
COLUMN
COLUMN tRCS tRCH
COLUMN tRCS
ROW tRRH
tRCS WE# V IH V IL
tRCH
tRCH
tAA tRAC tCAC tCLZ DQ V IOH V IOL OPEN tOE V IH V IL VALID DATA tOD tOFF tCLZ
tAA tCPA tCAC tOFF tCLZ VALID DATA tOD
tAA tCPA tCAC tOFF
tOE
tOE
VALID DATA tOD
OPEN
OE#
DON'T CARE UNDEFINED
FAST PAGE MODE TIMING PARAMETERS
-5 SYMBOL tAA
tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCPA tCRP tCSH tOD
-6 MAX 25 MIN 5 0 0 13 15 10 15 3 10 30 35 5 60 13 3 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOE
tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH
-5 MIN 3 30 50 13 8 50 18 0 0 30 0 13 125,000 15 10 60 20 0 0 40 0 15 MAX 13 13 MIN 3 35
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 40 0 0 8 13 3 8 5 50 3
10,000
125,000
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
EDO-PAGE-MODE READ CYCLE
tRASP V IH V IL tCSH tCRP CASL#/CASH# V IH V IL tAR tRAD tASR ADDR V IH V IL ROW tRCS WE# V IH V IL tAA tRAC tCAC tCLZ DQ V OH V OL OPEN tOE OE# V IH V IL tOES tOEP VALID DATA tAA tCPA tCAC tCOH VALID DATA tOD tOE tOES tCLZ tOEHC VALID DATA tOD tRAH tACH tASC COLUMN tCAH tACH tASC tCAH tACH tASC tCAH ROW tRCH tRRH tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP
RAS#
COLUMN
COLUMN
tAA tCPA tCAC
tOFF
OPEN
DON'T CARE UNDEFINED
EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL tAA tACH
tAR tASC tASR tCAC tCAH tCAS tCLZ tCOH tCP tCPA tCRP tCSH tOD tOE
-6 MAX 25 MIN 15 45 0 0 13 15 10 10,000 10 0 3 10 28 35 5 45 12 12 0 15 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOEHC tOEP
tOES tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH
-5 MIN 5 5 4 0 20 50 9 9 50 11 0 0 30 0 13 125,000 12 10 60 14 0 0 40 0 15 MAX MIN 10 5 5 0 25
-6 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 0 0 8 8 0 3 8 5 38 0
12
15 60
125,000
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
FAST/EDO-PAGE-MODE EARLY WRITE CYCLE 25
tRASP V IH V IL tCSH tCRP V IH V IL tAR tRAD tASR ADDR V IH V IL ROW tRAH tACH tASC COLUMN tCWL tWCH tWP WE# V IH V IL tWCR tDS V DQ V IOH IOL V IH V IL tDH tDS tDH tDS tRWL tDH tCAH tACH tASC tCAH tACH tASC tCAH ROW tCWL tWCH tWP tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP
RAS#
CASL#/CASH#
COLUMN tCWL tWCH tWP
COLUMN
tWCS
tWCS
tWCS
VALID DATA
VALID DATA
VALID DATA
OE#
DON'T CARE UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL tACH (EDO) tAR (EDO) tAR (FPM)
tASC tASR tCAH tCAS tCP tCRP tCSH tCSH
-6 MAX MIN 15 45 45 0 0 10,000 10,000 10 10 15 10 5 45 60 10 15 10 0 25 10,000 10,000 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tPC (FPM) tRAD (EDO) tRAD (FPM)
tRAH tRAH tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCR tWCS tWP (EDO) tWP (FPM)
-5 MIN 30 9 13 9 9 50 11 18 30 13 13 8 38 38 0 5 8 125,000 MAX MIN 35 12 15 10 10 60 14 20 40 15 15 10 45 45 0 5 10
-6 MAX UNITS ns ns ns ns ns 125,000 ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 40 0 0 8 8 13 8 5 38 50 8 13 8 0 20
(EDO) (FPM)
(EDO) tCAS (FPM)
(EDO) tRCD (FPM)
(EDO) (FPM) tCWL (EDO)
tCWL tDH tDS tPC (EDO)
(EDO) (FPM)
(FPM)
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
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4, 8 MEG x 64 DRAM SODIMMs
READ-WRITE CYCLE 25 (LATE WRITE and READ-MODIFY-WRITE cycles)
t RWC t RAS V IH V IL t CSH t RSH t CRP V IH V IL t AR t RAD t ASR ADDR V IH V IL t RAH t ASC t CAH t ACH t RCD t CAS t RP
RAS#
CAS#
ROW
COLUMN t RWD t RCS t CWD t AWD t CWL t RWL t WP
ROW
WE#
V IH V IL t AA t RAC t CAC t CLZ t DS VALID D OUT t OE V IH V IL t OD t DH
V DQ V IOH IOL
OPEN
VALID D IN t OEH
OPEN
OE#
DON'T CARE
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL tAA tACH (EDO) tAR (EDO) tAR (FPM) tASC tASR tAWD (EDO)
tAWD tCAC tCAH tCAS tCAS
UNDEFINED
-6 MAX 25 MIN 15 45 45 0 0 49 55 13 15 10 10 15 0 3 5 45 60 35 40 10 15 10 0 10,000 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOD (EDO) tOD (FPM) tOE (EDO) tOEH (EDO) tOEH (FPM)
tRAC tRAD tRAH tRAH tRAS tRCD tRCS tRP tRSH tRWC (EDO) tRWC tRWD tRWD tRWL tWP (EDO) tWP (FPM)
-5 MIN 0 3 8 13 50 9 13 9 8 50 11 18 0 30 13 116 131 67 73 13 5 8 10,000 12 15 10 10 60 14 20 0 40 15 140 155 79 85 15 5 10 MAX 12 13 12 MIN 0 3 10 15
-6 MAX 15 15 15 UNITS ns ns ns ns ns ns ns ns ns ns 10,000 ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 12 38 40 0 0 42 48 8 8 13 0 3 5 38 50 28 36 8 13 8 0
60
(FPM)
(EDO) tRAD (FPM) (EDO) (FPM)
(EDO)
10,000 10,000
(FPM) tCLZ (EDO)
tCLZ (FPM) tCRP tCSH tCSH
(EDO) tRCD (FPM)
(EDO)
(FPM) tCWD (EDO)
tCWD
(FPM) (EDO) (FPM)
(FPM) tCWL (EDO) tCWL (FPM)
tDH tDS
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
22
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
FAST/EDO-PAGE-MODE READ-WRITE CYCLE 25 (LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP V IH V IL tCSH tCRP CASL#/CASH# V IH V IL tRCD tCAS tCP tPC tPRWC NOTE 1 tCAS tCP tRSH tCAS tCP tRP RAS#
tASR ADDR V IH V IL ROW
tAR tRAD tRAH
tASC
tCAH COLUMN tRWD
tASC
tCAH
tASC
tCAH ROW tRWL
COLUMN
COLUMN
tRCS
tCWL tWP tAWD tCWD
tCWL tWP tAWD tCWD tAWD tCWD
tCWL tWP
WE#
V IH V IL tAA tRAC tDH tDS t CAC t CLZ tAA tCPA tCAC tCLZ VALID D OUT VALID D IN tOD tOE tOE VALID D OUT VALID D IN tOD tOE tDH tDS tAA tCPA tCAC tCLZ VALID D OUT VALID D IN tOD tOEH OPEN tDH tDS
DQ
V IOH V IOL
OPEN
OE#
V IH V IL
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL tAA tAR (EDO) tAR (FPM) tASC tASR tAWD (EDO) tAWD (FPM) tCAC tCAH
tCAS tCAS
DON'T CARE UNDEFINED
-6 MAX 25 MIN 45 45 0 0 49 55 13 15 10 10,000 10,000 10 15 0 3 10 28 30 35 35 5 45 60 35 40 10 15 10 0 10,000 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOD (EDO) tOD (FPM) tOE (EDO) tOE (FPM) tOEH (EDO) tOEH (FPM) tPC (EDO) tPC (FPM) tPRWC (EDO)
tPRWC tRAC tRAD tRAH tRAH tRASP tRCD tRCS tRP tRSH tRWD tRWL tWP (EDO) tWP (FPM)
-5 MIN 0 3 MAX 12 13 12 13 MIN 0 3
-6 MAX 15 15 15 15 UNITS ns ns ns ns ns ns ns ns ns ns 60 12 15 10 10 125,000 60 14 20 0 40 15 79 85 15 5 10 125,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 38 40 0 0 42 48 8 8 13 0 3 8
8 13 20 30 47 76 50 9 13 9 8 50 11 18 0 30 13 67 73 13 5 8
10 15 25 35 56 85
(EDO)
(FPM)
(FPM) tCLZ (EDO) tCLZ (FPM)
tCP tCPA (EDO) tCPA tCRP tCSH tCSH
(EDO) tRAD (FPM) (EDO) (FPM)
(FPM) (EDO) (FPM) (EDO) (FPM) (FPM) 5 38 50 28 36 8 13 8 0
(EDO) tRCD (FPM)
tCWD tCWD tCWL tDH tDS
tCWL (EDO)
(EDO) tRWD (FPM)
NOTE: 1. tPC is for LATE WRITE cycles only.
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
t RASP RAS# V IH V IL t CSH tPC tCRP CASL#/CASH# V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH ROW tASC tCAH t ASC t CAH tASC t ACH t CAH t RCD t CAS t CP t CAS tPC t CP tRSH t CAS t CP t RP
COLUMN (A) tRCS
COLUMN (B) tRCH
COLUMN (N) tWCS tWCH
ROW
WE#
V IH V IL tRAC
tAA tCPA tCAC
tAA
tCAC tCOH t WHZ VALID DOUT
t DS
t DH
DQ V IOH V IOL V IH V IL
OPEN tOE
VALID DOUT
VALID DIN
OE#
DON'T CARE UNDEFINED
EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL tAA tACH
tAR tASC tASR tCAC tCAH tCAS tCOH tCP tCPA tCRP tCSH tDH tDS
-6 MAX 25 MIN 15 45 0 0 13 15 10 10,000 10 3 10 28 35 5 45 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOE tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRSH tWCH tWCS tWHZ
-5 MIN 20 50 9 9 50 11 0 0 30 13 8 0 0 12 125,000 12 10 60 14 0 0 40 15 10 0 0 MAX 12 25 MIN
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns 15 ns ns
MIN 12 38 0 0 8 8 3 8 5 38 8 0
125,000
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
24
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
tRASP RAS# V IH V IL tRSH tCSH tCRP CASL#/CASH# V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC tCAH tASC tCAH tRCD tCAS tCP tPC tCAS tCP tRP
ROW
COLUMN
COLUMN tCWL tRWL tWCS tWP tWCH
ROW
tRCS
WE#
V IH V IL
tCAC t CLZ
NOTE 1 t OFF tDS VALID DATA
tDH
Q
V OH V OL
OPEN tAA tRAC
VALID DATA
OE#
V IH V IL
DON'T CARE UNDEFINED
FAST PAGE MODE TIMING PARAMETERS
-5 SYMBOL tAA
tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH tCWL tDH tDS
-6 MAX 25 MIN 45 0 0 13 15 10 10,000 15 3 10 5 60 15 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF tPC
tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWL tWCH tWCS tWP
-5 MIN 3 30 13 8 50 18 0 30 13 13 8 0 8 10,000 MAX 13 50 15 10 60 20 0 40 15 15 10 0 10 MIN 3 35
-6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN 40 0 0 8 13 3 8 5 50 13 8 0
125,000
NOTE: 1. Do not drive data prior to tristate.
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
25
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
EDO READ CYCLE (with WE#-controlled disable)
RAS# V IH V IL tCSH tCRP V IH V IL tAR tASR V IH V IL tRAD tRAH tASC tCAH tASC tRCD tCAS tCP
CASL#/CASH#
ADDR
ROW tRCS
COLUMN tRCH tWPZ tRCS
COLUMN
WE#
V IH V IL tAA tRAC tCAC tCLZ tWHZ tCLZ
DQ
V OH V OL
OPEN tOE
VALID DATA tOD
OPEN
OE#
V IH V IL
DON'T CARE UNDEFINED
EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL tAA tAR
tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH
-6 MAX 25 MIN 45 0 0 13 15 10 10 0 10 5 45 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOD tOE
tRAC tRAD tRAH tRCD tRCH tRCS tWHZ tWPZ
-5 MIN 0 MAX 12 12 50 9 9 11 0 0 0 10 12 12 10 14 0 0 0 10 MIN 0
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns 15 ns ns ns
MIN 38 0 0 8 8 0 8 5 38
10,000
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
26
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
RAS#-ONLY REFRESH CYCLE 25
t RC t RAS V IH V IL t CRP V IH V IL t ASR ADDR V IH V IL t RAH t RPC t RP
RAS#
CAS#
ROW
ROW
V DQ V OH OL V IH V IL
OPEN
WE#
DON'T CARE UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL tASR tCRP tRAH (EDO) tRAH (FPM) tRAS MIN 0 5 9 8 50 MAX MIN 0 5 10 10 60 -6 MAX UNITS ns ns ns ns ns SYMBOL tRC (FPM) tRC (EDO) tRP tRPC (FPM) tRPC (EDO) MIN 90 84 30 0 5 -5 MAX MIN 110 104 40 0 5 -6 MAX UNITS ns ns ns ns ns
10,000
10,000
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
27
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
SELF REFRESH CYCLE (Addresses and OE# = DON'T CARE)
tRP V IH V IL tRASS NOTE 1 (( )) (( )) tCSR tCHD (( )) (( )) (( )) tWRP tWRH (( )) (( )) OPEN tWRP tWRH tRPS NOTE 2
RAS#
tRPC tCP
tRPC tCP
(( ))
CAS#
V IH V IL
V DQ V OH OL V WE# V IH IL
CBR REFRESH CYCLE 25 (Addresses = DON'T CARE)
tRP RAS# V IH V IL tRPC tCP CAS# V IH V IL OPEN tWRP WE# V IH V IL tWRH tWRP tWRH tCSR tCHR tRPC tCSR tCHR tRAS tRP tRAS
V OH DQ V OL
DON'T CARE UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL
tCHD tCHR tCHR tCP tCSR tRAS tRASS tRP
-6 MAX MIN 15 15 10 10 5 10,000 60 100 40 10,000 MAX UNITS ns ns ns ns ns ns s ns SYMBOL tRPC (FPM) tRPC (EDO)
tRPS tWRH tWRN
-5 MIN 0 5 90 8 8 10 10 MAX MIN 0 5 105 10 10 10 10
-6 MAX UNITS ns ns ns ns ns ns ns
MIN 15 15 8 8 5 50 100 30
(FPM) (EDO)
(EDO) tWRP (EDO) (FPM)
tWRP (FPM)
NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed.
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
28
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
HIDDEN REFRESH CYCLE 20, 25 (WE# = HIGH)
tRC tRAS RAS# V IH V IL tCRP V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tCAH tRCD tRSH tCHR tRP tRAS
CASL#/CASH#
ADDR
ROW
COLUMN tAA tRAC tCAC tCLZ tOFF
DQx
V IOH V IOL
OPEN tOE
VALID DATA tOD
OPEN
OE#
V IH V IL
tORD
DON'T CARE UNDEFINED
FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS
-5 SYMBOL tAA tAR (EDO)
tAR
-6 MAX 25 MIN 45 45 0 0 13 15 10 15 10 3 0 5 13 12 12 13 3 0 15 15 15 15 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tOFF
-5 MIN 3 0 0 50 13 9 9 8 50 90 84 18 11 30 13 10,000 15 12 10 10 60 110 104 20 14 40 15 MAX 13 12 MIN 3 0 0 (FPM) tOFF (EDO)
tORD tRAC tRAD
-6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns 10,000 ns ns ns ns ns ns ns ns
MIN 38 40 0 0 8 15 8 3 0 5 3 0
(FPM)
tASC tASR tCAC tCAH tCHR
(FPM) (EDO) tRAH (EDO)
tRAD tRAH tRAS tRC
(FPM) tCHR (EDO)
tCLZ (FPM) tCLZ (EDO) tCRP tOD
(FPM)
(FPM) (FPM) (EDO)
tRC (EDO) tRCD tRCD tRP tRSH
(FPM) tOD (EDO)
tOE (EDO) tOE (FPM)
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
29
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
SPD EEPROM
tF t LOW t HIGH tR
SCL
t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO
SDA IN
t AA t DH t BUF
SDA OUT
UNDEFINED
SPD EEPROM TIMING PARAMETERS
SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA MIN 0.3 4.7 300 0 4 MAX 3.5 UNITS s s ns ns s s SYMBOL tHIGH tLOW tR tSU:DAT tSU:STA tSU:STO MIN 4 4.7 250 4.7 4.7 MAX UNITS s s s ns s s
1
300
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
30
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
144-PIN SODIMM DG-7 (32MB)
FRONT VIEW
2.667 (67.75) 2.656 (67.45) .079 (2.00) R (2X) 1.006 (25.55) 0.994 (25.25) .787 (20.00) TYP .236 (6.00) .100 (2.55) .157 (4.00) .043 (1.10) .035 (0.90) .150 (3.80) MAX
.071 (1.80) (2X)
.079 (2.00) .130 (3.30) (2X)
PIN 1
.059 (1.50) .024 (.60) TYP TYP 2.386 (60.60) 2.504 (63.60)
.0315 (.80) TYP
PIN 143 (PIN 144 ON BACKSIDE)
144-PIN SODIMM DG-8 (64MB)
FRONT VIEW
2.667 (67.75) 2.656 (67.45) .150 (3.80) MAX
.079 (2.00) R (2X) 1.006 (25.55) 0.994 (25.25) .787 (20.00) TYP .236 (6.00) .100 (2.55) .157 (4.00) .043 (1.10) .035 (0.90)
.071 (1.80) (2X)
.079 (2.00) .130 (3.30) (2X)
PIN 1
.059 (1.50) .024 (.60) TYP TYP 2.386 (60.60) 2.504 (63.60)
.0315 (.80) TYP
PIN 143 (PIN 144 ON BACKSIDE)
NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
31
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.
4, 8 MEG x 64 DRAM SODIMMs
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc.
4, 8 Meg x 64 DRAM SODIMMs DM83.p65 - Rev. 2/99
32
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999, Micron Technology, Inc.

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